PARADE: PARAmetric Delay Evaluation under Process Variation

Under manufacturing process variation, the circuit delay varies with process parameters. For delay test and timing verification under process variation, it is necessary to model the variational delay as a function of process variables. However, conventional methods to generate such functions are either slow or inaccurate. In this paper, we present a number of new methods for fast parametric delay evaluation under process variation. Our methods are based on explicit delay formulae or characterized lookup tables, and are significantly faster than conventional RSM method of comparable accuracy. Due to the efficiency of our method, we can accurately model any path delay as a function of multiple interconnect and device process variables in large circuits. Experimental results on ISCAS85 circuits show that the path delay error predicted by our methods is less than 3% of that computed by the RSM using SPICE, where the path delay variation is within ±10%.